As the geometries of semiconductor devices and particularly MOS transistors are being scaled to continually shorter gate lengths, there is a requirement for reduction in short channel effects. It is known that these short channel effects can be reduced by the use of non-uniform doping levels in the channel region. One manner of obtaining such non-uniform doping levels in the channel region has been by the use of halo implants. A halo implant involves the introduction of an implant which is at an angle of from about 10 to about 80 degrees and preferably about 10 to 40 degrees relative to a normal to the substrate surface. The halo implant is of opposite conductivity type to that of the source/drain region, is directed partially under the gate electrode and uses the gate electrode as a mask. In this manner, a halo region is formed which abuts the source/drain region as well as the gate oxide, is within the channel region and extends under the gate electrode, to provide a region between the source/drain region and the channel region which is more highly doped than the channel region and of like conductivity type.
Thus, to minimize short channel effects and improve device performance in today's transistor devices, halo implants are used. While the halo implant effectively suppresses punch through from the source to the drain, it unfortunately causes increased parasitic junction capacitance, which has a huge impact on the overall device and circuit performance. Two known parasitic junction capacitances caused by the halo implant include the source/drain bottom wall junction capacitance (Cjbot) and the source/drain gate sidewall junction capacitance (Cjgsw).
Turning Briefly to Prior Art FIG. 1, illustrated is a standard semiconductor device 100 having both the source/drain bottom wall junction capacitance (Cjbot) and the source/drain gate sidewall junction capacitance (Cjgsw). For illustration purposes, the standard semiconductor device 100 illustrated in FIG. 1 includes a substrate 110, a well 120 and a gate structure 130, including a gate 134, a gate oxide 136 and gate sidewall spacers 138. The standard semiconductor device 100 further includes halo implant regions 140 and source/drain regions 150. Often, conventional lightly doped compensation implants 160 are formed under the source/drain regions 150 to reduce the deep source/drain bottom wall junction capacitance (Cjbot). The conventional lightly doped compensation implants 160 are implanted at an angle perpendicular to the surface of the substrate 110, and are located between the higher doped source/drain regions 150 and the oppositely doped substrate 110. The perpendicular implantation of the lightly doped compensation implants are typically needed to produce an implant channeling tail for lowering the Cjbot.
Essentially, the conventional lightly doped compensation implants 160 form a grating or a buffer between these two regions thereby increasing the depletion junction at the bottom of the source/drain regions 150. This grating or buffer reduces the deep source/drain bottom wall junction capacitance (Cjbot) created between the higher doped source/drain regions 150 and the oppositely doped well 120. Unfortunately, the conventional lightly doped compensation implants 160 do little to reduce the source/drain gate sidewall junction capacitance (Cjgsw). Similarly, there is nothing known in the art that might help reduce the source/drain gate sidewall junction capacitance (Cjgsw).
Accordingly, what is needed in the art is a semiconductor device and method of manufacture therefor that has a reduced source/drain gate sidewall junction capacitance (Cjgsw).